Also, even if the PCIe interface is not being used, you cannot remove or reassign these pins in the constraint file. Specifically, changing the I/O interface of the FPGA in any way (do not remove any of the I/O for the PCIe interface, such as x300_pcie_int and LvFpga_Chinch_Interface), or modifying the pin and timing constraint files, could result in physical damage to other components on the motherboard, external to the FPGA, and doing this will void the warranty. However, certain modifications may result in either bricking the device, or even in physical damage to the unit.
Rfx 150 schematic code#
The Verilog code for the FPGA in the USRP X300 and USRP X310 is open-source, and users are free to modify and customize it for their needs. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. This information is current as of UHD 3.9.4 and was taken directly from Xilinx Vivado 2014.4. Utilization statistics are subject to change between UHD releases.Location information can be parsed out of the gps_gpgga sensor by using gpsd or another NMEA parser. You can query the lock status with the gps_locked sensor, as well as obtain raw NMEA sentences using the gps_gprmc, and gps_gpgga sensors.
Monolithic Synchronous Step-Down Regulator X300/X310 Schematics Key Component Datasheets Part Number This can be done in C++ using libraries such as Liquid DSP, or can be done in GNU Radio, in which there are three blocks that perform sampling rate conversion.Įnvironmental Specifications Operating Temperature Range If the desired sampling rate is not directly supported by the hardware, then it will be necessary to re-sample in software. An odd decimation factor will result in additional unwanted attenuation (roll-off from the CIC filter in the DUC and DDC blocks in the FPGA). Ideally, this decimation factor should be an even number. The sampling rate must be an integer decimation rate of the MCR. There are two master clock rates (MCR) supported on the X300 and X310: 200.0 MHz and 184.32 MHz. Ettus Research recommends to always use the latest stable version of UHD.RF Specifications RF Performance Data (with SBX-120)
Multiple high-speed interfaces (Dual 10G, PCIe Express, ExpressCard, Dual 1G).Two wide-bandwidth RF daughterboard slots.Frequency range: DC - 6 GHz with suitable daughterboard.
The hardware architecture combines two extended-bandwidth daughterboard slots covering DC – 6 GHz with up to 160 MHz of baseband bandwidth, multiple high-speed interface options (PCIe, dual 10 GigE, dual 1 GigE), and a large user-programmable Kintex-7 FPGA in a convenient desktop or rack-mountable half-wide 1U form factor.
Rfx 150 schematic software#
The Ettus Research USRP X310 is a high-performance, scalable software defined radio (SDR) platform for designing and deploying next generation wireless communications systems. 26 Guidance on 10Gb SFP+ to RJ45 Adapters.25 Guidance on SFP+ Adapters for Fiber Connectivity on USRP X300/X310.22 Option: General Purpose Input/Output (GPIO) Kit.20 Option: GPS Disciplined, Oven-Controlled Oscillator (GPSDO).
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